Many power circuits used for control or conversion of large amounts of power require that two switches be connected in series across a bulk voltage bus. This allows the chopping of a DC level into an alternating voltage for driving some form of load with inductive characteristics that are inherent in the load or are parasitic components of the connection to the load. Many concerns must be addressed when using this type of circuit. Error in the control of such a power stage can result in very high power loss in the commutating switch device. These measures involve the elimination of simultaneous conduction of the upper and lower switch stages caused by a variety of voltage and current slew rates interacting with either the power device or the control circuit through some stray capacitive or magnetic coupling. Many of these techniques are well understood and have brought about the widespread use of bridge circuits in high power applications.
The introduction of power MOSFET devices (defined herein as an electronic part that contains one or more active elements, such as a transistor or integrated circuit) has led to a new set of concerns with the parasitic source-to-drain diode that is inherent in the MOSFET's fabrication. The problem is referred to as the "dv/dt" problem or "commutating SOA"(safe operating area). Under most circumstances or circuit topologies, the dynamic dv/dt problem is simply not a problem. The condition under which concern is warranted is when the load has inductive characteristics with a lagging current and the current does not reverse within the period of the switching cycle.
Examples of circuits with potential commutation problems are PWM brushless motor controllers, DC-AC inverters that construct AC waveforms of much lower frequency than the switching frequency, and switching power amplifiers. These circuits have the condition where the parasitic diode in the MOSFET device may never come out of conduction before the other device turns on again, which leads to a reverse recovery of the conduction parasitic diode. The high level of current, combined with the high level of voltage across the device toward the end of the recovery (when the current is highest), causes what is known as dv/dt failure.
The parasitic diode in the power MOSFET is actually the base-collector junction of a parasitic bipolar transistor that exists due to the fabrication of the power MOSFET. This parasitic bipolar transistor 1 is in parallel with FET 3 as shown in Q.sub.1 in FIG. 1. The upper and lower devices, Q.sub.1 and Q.sub.2, are switched with pulse-width-modulated drive circuit 5 to control the bus voltage applied to a load Z. When one device Q.sub.2 is switched OFF at t.sub.o, current flows in the upper device Q.sub.1 in the manner shown in the waveforms of FIG. 2. The inductive fly-back causes the voltage at the load terminal to exceed the positive rail voltage. This would force current into resistor R.sub.B1 and the base-to-collector diode of the parasitic transistor 1 of Q.sub.1 and back into the positive rail. The slew rate of the voltage can be determined from the following relationship: ##EQU1##
The recovery period starts at t.sub.1 as the base of the parasitic transistor 1 becomes sufficiently charge with minority-carriers (from the collector) and with the discharge current (from C.sub.OB). The base-emitter junction becomes forward biased at this point, and the conditions for a secondary breakdown at t.sub.2 are set. A significantly more serious situation can arise if the lower device Q.sub.2 is switched on at t.sub.1 The bulk supply voltage would then be applied across the two conducting devices Q.sub.1 and Q.sub.2 causing an extremely high di/dt to be experienced by them and resulting in possible failure of one or both. The resistance in this Q.sub.1 is the base-emitter R.sub.B1 of the parasitic transistor 1 which is required to be as small as possible to avoid forward biasing the transistor. However, the low value of R.sub.B1 actually increases the di/dt that can be experienced by the devices Q.sub.1 and Q.sub.2.
Hence, even though the problem is commonly known as a dv/dt problem, it is equally as much a di/dt problem.
Since this unique failure mode was identified, several solutions have been suggested. The following are representative
One proposed solution is to use devices that are rated at voltages significantly higher than the bus voltage. The R.sub.DS (on) of MOSFET devices tends to increase with voltage rating, resulting in a serious penalty. It should also be noted that the breakdown voltage BV.sub.CEO of the parasitic transistors is about half of the corresponding BV.sub.DSS of the MOSFET device.
Another proposal illustrated in FIG. 3 is to add a Schottky rectifier diode 11 in series with Q.sub.1 and Q.sub.2 and a fast recovery diode 13 in reverse parallel to Q.sub.1 and Schottky combination. Unfortunately, the addition of Schottky diode 11 adds power loss to the other losses at load current and reduces the efficiency of the circuit. A possible problem can still result from the current fed by the high capacitance of the Schottky diode 11 into Q.sub.1 during the flyback period to t.sub.l.
Another proposal illustrated in FIG. 4 is to add a slow recovery diode 15 in series with an external voltage source 17. However, the penalty of additional parts and voltage source 17 is a significant factor in this scheme.
Many methods have been proposed for control of the above detrimental effects on MOSFET devices, but heretofore none have offered a quantitative design tool providing predictable control.
Another problem is extending the current range of the switching circuit when operating voltages exceed approximately 200 volts. The forward resistance of the device is one of the factors which determine the current load capacity. If the forward resistance is reduced, the current load capacity is increased.